New optical functionalities for on-chip transmission and signal processing

This challenge will explore the potential of on-chip all-optical signal processing functionalities for high throughput interconnects. In particular, feasibility studies of optical switching in resonant structures, including micro- and nano-cavities will be conducted. The ultimate goal is to identify nonlinear processing functions that, together with wavelength and spatial multiplexing, can benefit the implementation and operation of interconnects in 3D many-core architecture and provide the expected orders of magnitude improvements in throughput.

 

Roles of the participants

The proof-of-concept demonstrations of new switching functionalities will be performed by FOTON-Photonic Systems and INL based on inputs on the needs and requirements by INRIA. The work will also involve partners external to the 3D-Optical-ManyCores project (via existing and future collaboration projects), through which a number of devices will be made available. The outcome of the feasibility studies, and a thorough comparison of the technologies in terms of signal requirement, switching speed, energy consumption etc, will then be made available to INRIA for refined architecture studies.

 

Description

Optical solutions are attractive to provide the required throughput in 3D many-cores architectures. Massive transport of information has been demonstrated in optical communications in excess of 100 Tbit/s using WDM and even more than 1 Tbit/s using a single laser. It is clear that the introduction of high-speed on-chip modulation (using e.g. silicon modulators) and WDM technologies would also provide orders of magnitude improvements in throughput for interconnects, provided conditions are met with respect to energy consumption and footprint. Low-latency operation could benefit from the introduction of conceptually simple optical processing functionalities such as switching. In this context, a number of proof-of-concept switching experiments have been reported in structures whose length scales are compatible with on-chip applications, including nanowires and micro- or nano-cavities[1].

 

However, a number of challenges remain:

  • Switching is expected to take place in structures that are compliant with the silicon platform. This includes not only the integration of the nonlinear medium (resonant or non-resonant), but also the possibility to generate signals and pump pulses with proper specifications in terms of pulse duration and power. Most on-chip switching demonstrations so far have been performed with external pulse sources.
  • Until now, on-chip switching has essentially been demonstrated using low duty cycle pump and probe signals, a condition which is fundamentally different from the high duty cycles required to maximize the throughput in optical interconnects. A notable exception is the switching demonstration in hybrid III-V on silicon device by FOTON_Photonic Systems in the European project Copernicus [2]
  • The studies conducted so-far have focused on the feasibility of switching and on a better physical understanding of the processes involved through e.g. pump-probe experiments. However the benefit of optical switching will only be fully assessed if switching considerations are included in the chip design thanks to interactions with architecture studies. One of the originalities of the 3D-Optical ManyCores project is to finally allow this interaction by gathering optical signal processing and architecture experts.

 

We will address those challenges as follows in this part of the project. It is clear that the work is of an exploratory nature and will rely on FOTON-Photonic System’s recognized expertise in photonic subsystems for optical communications[3][4].

 

Our main goal is to tighten the link with the architecture studies in order to speak a common language and increase mutual understanding, assess the requirements imposed by prospective feasible architectures on the optical layer, and in turn report on the feasibility and requirements back to the architecture studies. Interactions with Challenge 2 on the specification of silicon-compliant light sources will also be essential, as well as with Challenge 3 in term of modeling and simulation of the architecture involving optical processing functionalities.

 

The technical approach will be as follows:

  • Potential switching technologies, and how they can be associated with the optical transport solutions suitable for many-core architectures, will be reviewed and assessed. A fair and systematic comparison of potential nonlinear media used for on-chip nonlinear processing is largely missing from the literature and will be conducted in order to abstract, among others, the energy requirements, footprint, and bit-rate scalability. The work will rely on literature studies and, whenever needed, experimental characterizations. FOTON-Photonic Systems and INL will be involved in this activity.
  • Realistic scenarios where optical processing may constitute an advantage will be defined in collaboration between FOTON-Photonic Systems, INRIA and INL. This is one of the major added values of this project, where optical signal processing will not only be demonstrated for its own sake, but also with respect to the architectures it will ultimately integrate to.
  • Advances in the design of processors and accelerators considered in the electrical layers of the 3D architecture rely on the CMOS fabrication process and are thus limited by transistor switching time and power dissipation. We will study the use of on-chip optical resources to offer an attractive alternative to slow and power consuming computing circuits. This will lead to the integration of interconnect and computing resources on the optical layer that would be suitable to accelerate the execution of data intensive application as the data propagate on the optical interconnect. For this purpose, we will further investigate the potential of OLUT (i.e. an optical core implementation of look up tables proposed by INL[5],[6]) to perform optical computation at relatively low joule/bit operation. In these papers, we take advantage of the electro-optical properties of semiconductors but an all-optical of such logical gates can be envisioned in the scope of the collaboration with FOTON and will be investigated in this project.
  • In parallel, theoretical and experimental studies of key optical functions will be conducted. Those include considerations on how compliant WDM optical sources, for instance quantum dot InP-based mode-locked lasers[7] either externally coupled to the microprocessors or bonded on silicon, which are commonly developed and studied at FOTON-Photonic Systems and OHM (see Challenge 2), can be used in signal processing applications. Micro-resonator based optical functions[8],[9],[10], for which FOTON-Photonic Systems has an expertise in micro-sphere as well as in micro-rings using polymer or semiconductor technology will be investigated. Photonic crystal planar waveguides[11] and cavities may also constitute a promising solution to scale down the size of photonic functions. It should be noted that the components that will be used in this framework will be available from other collaborative projects, for instance ANR ANTARES, TELDOT for the InP mode-locked lasers, ANR CALIN and ANR ORA for the micro-resonators, and FP7 COPERNICUS for the photonic crystal components. Ultimately, devices realized in Challenge 2 will be used for integration into the demonstration of signal processing functionalities.
  • The integration of multi-wavelength sources on the silicon platform is facing a number of challenges, as addressed in Challenge 2. A complementary solution to enhance the throughput of on-chip interconnects is to use mode-multiplexing in multimode waveguides[12]. Some optical processing functionalities that are compatible with both wavelength and mode-multiplexing have been recently demonstrated[13]. The generation of highly stable sources using wave-mixing is also under study and is the object of a proposal to the ANR. However, how to take advantage of both wavelength and mode multiplexing for concrete architectures is unclear at the present time and will be studied further in this project.
  • Finally, based on the prospective theoretical and experimental studies of nonlinear processing, feedback will be provided for refined architecture studies by INRIA.

 

Throughout this challenge we will establish distinctions between the solutions based on their maturity and immediate or longer-term applicability. More than performing a scientific monitoring of the different photonic integration solutions (e.g. polymers, Si/Silica, silicon nitride, InP, GaP etc), we will contribute to the development of component and photonic function libraries for the design of ONoCs in Challenge 3, such as models of laser sources, routers, all-optical memories or wavelength converters. The aim of this task is to evaluate the potential and efficiency of different components and approaches from the photonics side. The success of this task requires a strong interaction with INRIA and INL who will investigate new ONoC architectures. From these investigations, specifications will be elaborated by the consortium, identifying the needs for the introduction of photonics in these new architectures. Particular attention will be brought to the energy consumption and to the down-law scaling.



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[2] K. Lenglé, M. Gay, A. Bazin, I. Sagnes, R. Braive, P. Monnier, L. Bramerie, T. N. Nguyen, C. Pareige, R. Madec, J.  C. Simon, R. Raj, and F. Raineri, “Fast all-optical 10 Gb/s NRZ wavelength conversion and power limiting function using hybrid InP on SOI nanocavity” Eur. Conf. Opt. Commun. (2012) We.2.E.5.

[3] Q. Thai Nguyen, P. Besnard, L. Bramerie, A. Shen, C. Kazmierski, P. Chanclou, G.-H. Duan, and J.-C. Simon, “Bidirectional 2.5-Gb/s WDM-PON using FP-LDs wavelength-locked by a multiple-wavelength seeding source based on a mode-locked laser,” IEEE Photon. Technol. Lett. 22 (2010) 733 (2010).

[4] Y. Ben M’Sallem, Q. T. Le, L. Bramerie, Q.-T. Nguyen, E. Borgne, P. Besnard, S. LaRochelle, L. A. Rusch, and J.‑C. Simon, “Quantum-dash mode-locked laser as source with 56 Gbit/s DQPSK modulation for WDM multicast application,” IEEE Photon.Technol.Lett. 23 (2011) 453.

[5] S. Le Beux, Z. Li, C. Monat, X. Letartre, and I. O’Connor, “Reconfigurable photonic switching: towards all-optical FPGAs,” 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC), Istanbul, Turquey, 2013.

[6] Z. Li, S.Le Beux, C. Monat, I.O’Connor, and X. Letartre, “Optical look up table,” IEEE Int. Conf. Design Automation and Test in Europe (DATE) (2013).

[7] K. Klaime, R. Piron, C. Paranthoen, T. Batte, F. Grillot, O. Dehaese, S. Loualiche, A. Le Corre, R. Rosales, K. Merghem, A. Martinez and A. Ramdane “ 20 GHz to 83 GHz single section InAs/InP quantum dot mode-locked lasers grown on (001) InP misoriented substrate,” Int. Conf. Indium Phosphide and Related Materials, IPRM (2012).

[8] Y. Dumeige, “Time-domain analysis of resonator array buffers”, IEEE Photon. Technol. Lett. 21 (2009) 435.

[9] S Trebaol, A. Rasoloniaina, Y. Dumeige, and P. Féron, “Effects in high-Q whispering gallery mode resonators: modelling and applications” Int. Conf. Transparent Optical Networks , ICTON (2011).

[10] Y. Dumeige, and P. Féron, “Stability and time-domain analysis of the dispersive tristability in microresonators under modal coupling”, Phys. Rev. A 84 (2011) 043847.

[11] S. Malaguti, A. Armaroli, G. Bellanca, S. Trillo, S. Kaunga-Nyirenda, J. Lim, E. Larkins, P. T. Kristensen, K. Yvind, J. Mørk et al, “Numerical modeling in photonic crystals integrated technology: the COPERNICUS project,” Int.Conf. Num. Simul.of Optoelectronic Devices, NUSOD, (2011).

[12] Y. Ding, J. Xu, F. Da Ros, B. Huang, H. Ou, and C. Peucheret, “On-chip two-mode division multiplexing using tapered directional coupler-based mode multiplexer and demultiplexer,” Opt. Express 21 (2013) 10376.

[13] Y. Ding, J. Xu, H. Ou, and C. Peucheret, “Mode-selective wavelength conversion based on four-wave mixing in a multimode silicon waveguide,” to appear Opt. Express, 2013.