Design space exploration of 3D architectures using Optical Network-on-Chip (ONoC)
The global objective of this challenge consists in providing a generic model of 3D architectures based on a new version of an ONoC, and to propose a design space exploration infrastructure that can help the designer to compare the global performance of an application implemented on different architecture alternatives. The communication infrastructure will be defined from application requirements and will be able to support exchanges between heterogeneous execution resources through optical communication devices.
INL + INRIA
A novel ONoC will be defined according to the communication requirement of the architecture. Indeed, the ONoC will have to manage heterogeneous communications such as i) processor to processor (e.g. for broadcasting data/instructions), ii) processor to/from accelerator for data exchange and also iii) memory to accelerator (for instruction/bitstream loading). Managing both unidirectional (unicast and multicast) and bidirectional communications in the same network could lead to a drastically large and energy inefficient interconnect solution. Hence, design trade-offs need to be explored in order to propose a power aware ONoC that best suits expected performance requirements of the heterogeneous communication infrastructure. For this purpose, models of elementary components designed in the device-level tasks will be used and carefully integrated into the ONoC design by considering their characteristics (e.g. power and size). Taking into account such characteristics will also allow the area and power overhead of the electrical layers to be evaluated by considering, for instance, the current to be driven in the TSV to modulate the laser sources.
This design space exploration could therefore lead to the modification of:
- The number or the type (dedicated or shared) of network access ports per layer, which will impact the ONoC size, which in turn will impact its power and performances characteristics.
- The communication protocol, which will directly impact ONoC energy and performances characteristics.
- The communication service of the operating system, which will impact the way the network is used, without affecting its performances and power properties.
- The placement of tasks into the complete system, which can be more flexible if the communication cost, can be reduced without affecting the performances.
- The application level that can be modified in order to better exploit the ONoC capabilities (e.g using real broadcasting communication rather than duplication of communications).
To support such design space exploration step, a set of simulation approaches will be developed to address two different abstraction levels that will be used at different design steps. Design exploration is generally performed at a high level, but based on low-level characterization of components. The project will therefore address these two levels by proposing a first simulation tool, which helps the designer to characterize the optical components and extract high-level models. These high-level models will be used in a second simulation tool, which performs system simulations to verify the global performance provided by the heterogeneous integration of optical and electrical layers
It is worth noticing that the design space exploration challenge will be carried out by continuously considering the novel photonic devices properties and the novel optical functions respectively defined in Challenges 2 and 4 (this is achieved through regular updates of the ONoC in the modeling challenge, i.e. Challenge 3). Furthermore, design space exploration results will allow i) highlighting characteristics of novel devices needing improvements (e.g. optical link bandwidth), and ii) evaluating interests of proposed novel optical functions.